Power consumption is one of the major problems faced by the semiconductor industry. Conventionally, only dynamic power has been a significant source of power consumption. However, with the advancements in shrinking processor technology, the static power is also posing new challenges in microcontroller design.
Every CMOS digital circuit has a Minimum Leakage Vector (MLV) corresponding to which the circuit consumes the lowest amount of leakage power. This MLV corresponds to a specific vector set from the entire number of digital states that the logic can be in, considering all sequential elements and primary inputs. Identification of a minimum leakage vector (MLV) is an important problem in low power design of VLSI circuits. Unlike dynamic power, which depends on the average number of switching transistors per clock cycle, the leakage power depends on the number of on chip transistors, regardless of their average switching activity. The input pattern dependence of the leakage current makes the problem of determining the leakage power dissipated by a circuit a difficult one. This is because by applying the minimum leakage producing input combination to the circuit, when it is in the idle mode, the leakage power dissipation of the circuit can be reduced significantly. It is assumed that by using many of the known techniques and tools an MLV can be generated for each peripheral for use by the power control module (PCM).
FIG. 1 illustrates a block diagram of a conventional system 100 on chip (SoC) topology. The system 100 includes a core processor 102 that could be a typical high performance RISC/CISC CPU with a system bus interface 104, connected to the system bus infrastructure 106, a system bus to peripheral bus protocol conversion bridge 108, multiple peripherals such as 110A and 110B that are placed on a peripheral bus infrastructure 112 each containing its own peripheral bus interface 114A and 114B, a native or system bus interface 116 coupled from the core CPU 102 to a system ROM 118 and (or) a system RAM memory 120. The power supply for the system 100 is through a central voltage regulation unit 122. During a normal operation of the system 100, the core CPU 102 executes instructions by reading data from the ROM 118 or the RAM 120 memories through the native or system bus interface 116.
For SoC architectures, some conventional power reduction schemes like, clock gating, dynamic voltage scaling or power down approaches are solely focused upon the dynamic power reduction. The power domain creation method involves the classification of logic domains that will be active in various modes of operation of a device, like, a normal run mode and a standby mode of operation.
FIG. 2 illustrates a block diagram of a conventional system on chip (SoC) 200 having logic domains for different modes of operation. The voltage regulator supplies through supply pad 202. In the normal mode, the normal mode regulator maintains the supply to the normal and standby logic. During standby mode, power supply to the logic that remains inactive during standby mode is shut down using an analog switch 210 and the standby mode regulator maintains supply into this domain and the normal mode logic is powered down creating a power domain. This reduces the leakage current during the standby mode; however, it does not address the issue of leakage during normal run mode. Also, a large number of on chip analog switches are to be used which consume much larger area.
In the peripheral clock gating, the clock to the peripherals is gated with a control signal (clock_gate) that is used to gate the peripheral clock (pclk) using an AND gate. FIG. 3 illustrates a block diagram of a peripheral clock gating. The clock gated peripheral retains it previous state of operation until the gate signal request is cleared. This approach addresses the issue of dynamic power reduction only and not the static power consumption.
It is assumed that the SoC has two modes of operations, namely a normal run mode of operation wherein a typical application program is placed in the ROM or RAM memories and many of the SoC peripherals may remain unused. Conventional approaches to control system power consumption during the normal run mode focus solely on reducing dynamic power consumption and none of them address the issue of static power reduction in the form of leakage power reduction. At low process technologies, static power consumption levels, in the form of leakage current, approach dynamic power consumption levels and forms critical component of the consumed power. The other approach discussed addresses the issue of static and dynamic power consumption by the esoteric means of switching off the power supply to the core logic. This method increases the latency of the system, as the core logic must be reprogrammed through the system RAM or ROM on wakeup. The programming procedure cannot commence until and unless the system clock generation unit stabilizes and outputs a clock of constant phase and frequency which further adds to the system latency.
Therefore, there is a need for a novel architecture and method for simultaneously controlling the static as well as the dynamic power consumption of an SoC, while maintaining a balance between the system latency and throughput.